SAT-Based Scalable Formal Verification Solutions

An Integrated Approach for Combining BDDs and SAT Provers

Many formal verification tools today are based on Boolean proof techniques. The two most powerful approaches in this context are Binary Decision Diagrams (BDDs) and methods based on Boolean Satisfiability (SAT). Recent studies have shown that BDDs and SAT are orthogonal, i.e. there exist problems where BDDs work well, while SAT solvers fail and vice versa. Beside this, the techniques are very d...

A Scalable Algorithm for Minimal Unsatisfiable Core Extraction

We propose a new algorithm for minimal unsatisfiable core extraction, based on a deeper exploration of resolution-refutation properties. We provide experimental results on formal verification benchmarks confirming that our algorithm finds smaller cores than suboptimal algorithms; and that it runs faster than those algorithms that guarantee minimality of the core. (A more complete version of thi...

Verification of Building Blocks for Asynchronous Circuits

Scalable formal verification constitutes an important challenge for the design of asynchronous circuits. Deadlock freedom is a property that is desired but hard to verify. It is an emergent property that has to be verified monolithically. We present our approach to using ACL2 to verify necessary and sufficient conditions over asynchronous delay-insensitive primitives. These conditions are used ...

Strategies for SAT-Based Formal Verification

Eureka-2008 SAT Solver

We describe the SAT solver Eureka. Eureka is a state-of-the-art SAT solver, used in various Formal Verification flows at Intel. Eureka is based upon backtrack search DLL algorithm, enhanced by failure-driven assertion loop; nonstandard conflict analyses; restart and clause deletion strategies; CBH decision heuristic and decision stack shrinking.